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    <title>Ben Blaxill</title>
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    <lastBuildDate>Mon, 18 Mar 2019 00:00:00 +0000</lastBuildDate>
    
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      <title>Compdata Trees and Catamorphisms</title>
      <link>https://blaxill.org/posts/compdata-trees-and-catamorphisms/</link>
      <pubDate>Mon, 18 Mar 2019 00:00:00 +0000</pubDate>
      <author>blog@blaxill.org (Ben Blaxill)</author>
      <guid>https://blaxill.org/posts/compdata-trees-and-catamorphisms/</guid>
      <description>Data types a la carte and in particular P. Bahr and T. Hvitved&amp;rsquo;s implementation compdata provide a way to create extensible data types and a library of recursion schemes ready to use on them. Compositional data types and recursion schemes are useful tools for manipulating recursive structures that under go structural changes while retaining some shape/data through different passes such compiler passes on tree types.
I&amp;rsquo;m going to go through a example of using compdata to transform a simple expression tree by adding and removing timing annotation and delay nodes through recursion schemes.</description>
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      <title>Practical Type Configured Hashing Circuits</title>
      <link>https://blaxill.org/posts/practical-type-configured-hashing-circuits/</link>
      <pubDate>Tue, 05 Mar 2019 23:00:00 -0500</pubDate>
      <author>blog@blaxill.org (Ben Blaxill)</author>
      <guid>https://blaxill.org/posts/practical-type-configured-hashing-circuits/</guid>
      <description>hash-cores is an experimental library for building type configured FPGA hash cores. The intention is to provide a collection of RTL based hashing components that perform close to hand written verilog. Crypto mining is not a goal of the project, and the library design does not take into account memory hard targets.
From a Haskell perspective, I wanted to see how far type-level delay annotations on Clash DSignals could be taken, and hashing circuitry seemed a good fit as timing can mostly be statically determined.</description>
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